ETH is facing issues such as high gas fees and congestion, while ZK hardware acceleration can assist in achieving real-time proofs in peripheral conditions, meeting the requirements of ZKRollup. This article is sourced from an article written by “雨中狂睡” and compiled, translated, and written by PANews.
(Opener:
In-depth explanation of Based Rollup: How to solve the challenges faced by Optimistic and ZK
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(Context supplement:
What is the next step for Ethereum Layer2: How does ZK technology unleash new market potential?
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Opportunities in the blockchain often stem from “solving market demands.” How can we understand this? Let’s take an example that everyone can understand. During the previous cycle, DeFi Summer on ETH was hot, but it also led to problems such as high gas fees and congestion. BSC emerged during that period, and accordingly, many wealth opportunities arose.
In addition to BSC, there are other well-known opportunities such as Solana, Avalanche, and other Alt-Layer1 solutions.
The same goes for NFT Summer. With the rise in ETH prices, the market urgently needs new wealth opportunities in the ecosystem to earn and accumulate ETH, or in other words, leverage ETH. Therefore, NFT became the hot spot.
What is ZK hardware acceleration?
The same applies to ZK hardware acceleration. ZK hardware acceleration aims to solve the problem of “inefficient ZK-SNARK proof generation.”
During a previous conference, Vitalik Buterin mentioned that ZK-SNARK proof generation takes too long (about 20 minutes) and is inefficient. Ideally, real-time proofs would be preferable. In order to solve this problem, Vitalik Buterin proposed three solutions: “parallelization and aggregation trees,” “using SNARK algos and hash to enhance efficiency,” and “using ASIC for ZK hardware acceleration.”
From my understanding, the first two solutions aim to improve ZKP efficiency from a technological upgrade perspective, which takes time for improvement (to be honest, I don’t quite understand, so I can only understand it superficially). On the other hand, using “ASIC for ZK hardware acceleration” is like some people in the gaming world installing spirits into their mouse to solve the problem of low ZKP efficiency through peripherals.
ZK hardware acceleration can be divided into GPU, FPGA, and ASIC. Why did Vitalik Buterin specifically mention ASIC? It is because, from the perspective of flexibility, GPU > FPGA > ASIC, while from the perspective of performance, ASIC > FPGA > GPU.
In simple terms, GPU is general-purpose, while ASIC is custom-made and specialized. General-purpose means that everyone can use it, but its performance advantage is not so obvious. ASIC chips can only adapt to a single solution, and FPGA is in between ASIC and GPU, with a certain degree of flexibility and performance stronger than GPU but weaker than ASIC.
Overall, ASIC can provide higher computing efficiency for ZKP because the current ZKP proof technology is relatively fixed. If ZKRollup seeks ZK hardware acceleration, GPU is a general solution, but in the future, customized high-performance ASIC chips are obviously the optimal solution.
Currently, the leading project in ZK hardware acceleration is Cysic, led by Polychain.
Regarding Cysic, many people have provided detailed introductions. As a non-technical background person, I can only share my understanding. Friends who are interested in the technology itself can visit the official website or check media reports.
Cysic’s hardware acceleration solution consists of two parts: ZKVM+ hardware design (GPU+ASIC). Currently, Cysic provides GPU acceleration solutions to ZKRollup projects such as Scroll (Cysic has reserved nearly 100,000 GPU devices. Currently, Cysic’s advantage lies in sufficient GPU computing power, but the focus will shift to ASIC chips in the future).
ZKVM is a virtual machine environment that supports ZK circuits, and its main advantages are continuity and parallelism. In simple terms, when we deal with a large cake, high requirements are placed on computing devices, bandwidth, and memory. ZKVM allows us to cut the large cake into small pieces, making it more convenient for us to eat, with higher controllability and compatibility. And parallelism supports us in cutting and eating the cake at the same time, improving efficiency.
In terms of hardware design, Cysic packages the executor, which is used for calculations, with a certain number of ZKVM chips and other necessary hardware into one box. This way, the device’s flexibility in calculations and its portability in the physical world are improved.
In short, Cysic’s design is based on considerations of cost-effectiveness and energy efficiency.
Lastly, let me share my thoughts.
Why pay attention to the ZK hardware acceleration track? It is based on optimism about the future development of ZKRollup. ZK hardware acceleration can assist ZKP proofs in achieving real-time proofs in peripheral conditions, meeting the requirements of ZKRollup.
Therefore, when the ZKRollup narrative becomes hot, we can definitely take a look at projects related to ZK hardware, and there may be speculative opportunities at that time. Personally, I think it’s not too late to speculate when the ZK narrative starts to gain attention (which may be a bit difficult this year).
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